It is related to an output buffer circuit for a semiconductor device, and more particularly, to a three-state output buffer circuit.
Recent semiconductor devices have been configured so that internal circuits handle signals with lower levels than signals handled by external circuits to reduce power consumption. That is, the operation power supply voltage of the internal circuits is set lower at a level that is lower than that outside the semiconductor device. Therefore, the semiconductor device includes an output buffer circuit having a level converter that converts the signal level of the internal circuits to the external signal level.
A conventional output buffer circuit 100 for a semiconductor device that operates with two types of power supply voltage is described below with reference to FIG. 1.
The output buffer circuit 100 is a three-state type output buffer. The output buffer circuit 100 receives data input signal A and control input signal C from internal circuits (not shown in the drawing) of the semiconductor device and generates an output signal having one of three values, that is, an H level, an L level, or high impedance, based on the input signals A and C.
The output buffer circuit 100 includes a level converter unit 110, which converts the signal levels of the input signals A and C to a predetermined level to generate an intermediate signal, and an output circuit 130, which provides an external output terminal EX with an output signal OUT based on the intermediate signal generated by the level converter unit 110.
The level converter unit 110 includes a first level converter 110a and a second level converter 110b. The first level converter 110a receives the data input signal A from a core circuit that is operated by a power supply potential VDL of a semiconductor chip core. The first level converter 110a further receives an inversion signal A bar of the data input signal A. One of the signals A and A bar has a ground level (L level), and the other one of the signals A and A bar has the power supply potential VDL level (H level) of the semiconductor chip core. The first level converter 110a performs level conversion of the signals A and A bar having amplitudes from the ground level to the power supply potential VDL level of the semiconductor chip core to generate an intermediate signal B that has an amplitude from ground level to the power supply potential VDH level of an external output interface. Then, the first level converter 110a provides the intermediate signal B to the output circuit 130.
Specifically, when the data input signal A is set at an H level and the inversion signal A bar is set at an L level, a transistor TN11 is turned OFF and a transistor TN12 is turned ON. When the transistor TN12 is turned ON, the gate of transistor TP11 is connected to ground. This turns ON the transistor TP11. When the transistor TP11 is turned ON, the gate of a transistor TP12 is connected to the power supply potential of an external output interface. This turns OFF the transistor TP12. In this state, the potential at a node N11 between the transistors TN11 and TP11 is set to an H level power supply potential (VDH) of the external output interface, and an intermediate signal B having the H level power supply potential of the external output interface is provided from the node N11 to the output circuit 130.
Conversely, when the data input signal A is set at an L level and the inversion signal A bar is set at an H level, the transistor TN11 is turned ON and the transistor TN12 is turned OFF. When the transistor TN11 is turned ON, the gate of the transistor TP12 is connected to ground. This turns On the transistor TP12. When the transistor TP12 is turned ON, the gate of the transistor TP11 is connected to the power supply potential VDH of the external output interface. This turns OFF the transistor TP11. In this state, the potential of the node N11 is set at the ground level, and an intermediate signal B having the ground level (L level) is provided from the node N11 to the output circuit 130.
Similarly, the second level converter 110b receives a control input signal C and an inversion signal C bar from internal circuits. The second level converter 110b performs level conversion of the signals C and C bar that have amplitudes from ground level to power supply potential VDL level of the semiconductor chip core to generate an intermediate signal D that has an amplitude from ground level to the power supply potential VDH level of the external output interface. Then, the second level converter 110b provides the intermediate signal D to the output circuit 130.
The output circuit 130 includes a logic control circuit 140 and a final stage buffer 150. Based on the intermediate signals B and D received from the level converter unit 110, the logic control circuit 140 generates signals E and F having either the ground level or the power supply potential VDH level of the external output interface at the transistors TP50 and TN50 of the final stage buffer 150.
Specifically, when the intermediate signal D has a power supply potential VDH level of the external output interface (the control input signal C has a power supply potential VDL level of the semiconductor chip core), an H level (power supply potential VDH level of the external output interface) signal E is provided to the transistor TP50 and an L level (ground level) signal F is provided to the transistor TN50 regardless of whether the intermediate signal B has an H level or an L level. In this state, a node N50 between the transistors TP50 and TN50 is set at high impedance because both of the transistors TP50 and TN50 are turned OFF.
When the intermediate signal D has the ground level (the control input signal C has the ground level) and the intermediate signal B has the power supply potential VDH level of the external output interface (the data input signal A has the power supply potential VDL level of the semiconductor chip core), L level signals E and F are provided to the transistors TP50 and TN50. Since the transistor TP50 is turned ON and the transistor TN50 is turned OFF in this state, an output signal OUT that has a power supply potential VDH level (H level) of the external output interface is provided to an external output terminal EX.
Furthermore, when the intermediate signals D and B have the ground level (the data input signals A and C have the ground level), H level signals E and F are provided to the transistors TP50 and TN50. Since the transistor TP50 is turned OFF and the transistor TN50 is turned ON at this time, a ground level (L level) output signal OUT is provided from the node N50 to the external output terminal EX.
Japanese Laid-Open Patent Publication No. 10-285013 describes such a three-state type output buffer circuit.
In such an output buffer circuit 100, when the level converters 110a and 110b have different internal parasitic capacities, a signal delay skew occurs during power activation between the intermediate signal B generated by the first level converter 110a and the intermediate signal D generated by the second level converter 110b (refer to FIG. 2(b)). In particular, the intermediate signal B is delayed from the intermediate signal D when the parasitic capacitance of the first level converter 110a is greater than the parasitic capacitance of the second level converter 110b. The magnitude of the parasitic capacitance changes depending on the type of power supply wiring in an upper layer and the length of the wiring, which changes in accordance with the layout position of the elements such as transistors in the level converters 110a and 110b. The inventor of the present invention has found that such a signal delay skew generates an erroneous operation signal SH as shown in FIG. 2(d) as an output signal OUT.
A case in which an erroneous operation signal SH is generated when the level converter unit 110 receives an L level data input signal A and an L level control input signal C during power activation will now be discussed.
As shown in FIG. 2(a), during power activation, the power supply potential VDL of the semiconductor chip core and the power supply potential VDH of the external output interface each rise with a predetermined slope. Furthermore, the H level inversion signals A bar and C bar follow the rising level of the power supply potential VDL of the semiconductor chip core and also rise. In this state, the signal levels of the intermediate signals B and D generated by the level converters 110a and 110b follow the rising of the external output interface power supply potential VDH until the signal levels of the inversion signals A bar and C bar exceed the threshold voltages of the respective transistors TN11 and TN21, as shown in FIG. 2(b). Then, when the inversion signals A bar and C bar exceed the thresholds of the transistors TN11 and TN21, the transistors TN11 and TN21 are turned ON, and the intermediate signals B and D fall to the ground level (L level). However, the fall of the intermediate signal B is delayed relative to the intermediate signal D when the parasitic capacitance of the first level converter 110a is greater than the parasitic capacitance of the second level converter 110b , as previously described. The signal delay skew generated by the intermediate signals B and D is maintained by a racing in the buffer, and is also generated in the transistors TP50 and TN50 of the final stage buffer 150. That is, as shown in FIG. 2(c), a period occurs in which both the signals E and F that are provided to the transistors TP50 and TN50 are set at L level. Thus, since the P-channel MOS transistor TP50 is turned ON and the N-channel MOS transistor TN50 is turned OFF, and H level erroneous operation signal SH is momentarily generated as an output signal OUT, which follows the rising level of the external output interface power supply potential VDH, as shown in FIG. 2(d). Accordingly, there is a possibility that this erroneous operation signal SH may cause an erroneous operation during power activation.